Career

📍 Location: Bengaluru, Karnataka
📅 Experience: Freshers (College Passouts: 2022, 2023, 2024)
🎓 Qualification: B.Tech/BE in Electronics & Communication, M.Tech (2022/2023/2024)

Job Description:
DigiSilica is looking for highly motivated Analog Layout Engineers who are passionate about semiconductor design and eager to build a career in the VLSI industry. As part of our expert team, you will be involved in cutting-edge analog layout design projects, working on advanced CMOS technologies.

Key Responsibilities:

• Work on Analog & Mixed Signal Layout Design for high-performance circuits.
• Understand and implement CMOS Process Technology, including device physics.
• Perform layout design considering DRC, LVS, EM/IR, ESD, and LUP.
• Collaborate with senior engineers for circuit optimization & design improvements.
• Use industry-standard EDA tools for layout development and validation.

• Basic knowledge of CMOS devices & process technology
• Understanding of ESD (Electrostatic Discharge), LUP (Latch-Up), EM (Electromigration), IR drop
• Strong analytical and problem-solving skills
• Ability to work in a fast-paced semiconductor environment
• Knowledge of any layout tools (Virtuoso, Laker, or equivalent) is a plus

📍 Location: Bengaluru, Karnataka
📅 Experience: 3 to 5 years
🎓 Qualification: Bachelor/Master of Engineering in Electrical/Electronics

Job Description:
DigiSilica is seeking experienced Analog Layout Engineers with 3-5 years of expertise in custom layout design for high-performance analog/mixed-signal IPs. If you have a strong background in analog layout, IPs, high-speed designs, and advanced CMOS processes, this is an excellent opportunity to work on cutting-edge semiconductor technologies.

Key Responsibilities:

• Work on Analog & Mixed Signal Layout Design for advanced IP blocks, GPIOs, and high-speed circuits.
• Perform full-custom layout design at deep sub-micron nodes.
• Ensure LUP (Latch-Up), ESD (Electrostatic Discharge), EM (Electromigration), IR drop compliance.
• Handle floor-planning, placement, routing, and parasitic-aware layout design.
• Conduct DRC, LVS, and other physical verification checks.
• Collaborate with circuit design engineers for layout optimization and performance improvements.
• Utilize industry-leading EDA tools (Cadence Virtuoso, Mentor Calibre, Synopsys tools, etc.).

• 3-5 years of experience in Analog Layout Design
• Expertise in CMOS process technology, deep sub-micron nodes
• Experience with high-speed layouts, GPIOs, and IP-level design
• Knowledge of LUP, ESD, EMIR, parasitic effects, and reliability concerns
• Strong understanding of physical verification methodologies
• Familiarity with Tapeout processes & foundry guidelines
• Excellent problem-solving and debugging skills

📍 Location: Bengaluru, Karnataka
📅 Experience: 6 to 8 years
🎓 Qualification: Bachelor/Master of Engineering in Electrical/Electronics

Job Description:
DigiSilica is looking for a highly skilled Senior Analog Layout Engineer with 6-8 years of experience in FinFET technology nodes. This role requires expertise in analog layout design for complex IPs like ADCs, PLLs, LDOs, and other high-performance circuits. As a senior team member, you will play a key role in mentoring junior engineers, driving layout innovation, and ensuring compliance with industry standards.

Key Responsibilities:

• Lead and contribute to full-custom Analog & Mixed Signal Layout Design.
• Work on FinFET nodes (7nm, 5nm, 3nm, or below) for high-performance Analog IPs.
• Mentor and guide junior engineers, ensuring best practices in layout methodologies.
• Handle layout parasitics, ESD, LUP, EMIR, and reliability concerns.
• Collaborate with circuit designers for layout optimization & performance enhancement.
• Conduct floorplanning, placement, routing, and layout verification (DRC, LVS, ERC, ANT, PERC, etc.).
• Work with foundries and cross-functional teams to ensure design meets specifications.
• Utilize industry-standard EDA tools like Cadence Virtuoso, Synopsys IC Compiler, Mentor Calibre, etc.

• 6-8 years of experience in custom analog layout design
• Experience in FinFET nodes (7nm and below)
• Strong expertise in ADC, PLL, LDO, and other Analog IP layouts
• Proficiency in parasitic-aware layout design, EMIR, LUP, ESD compliance
• Strong leadership skills to mentor and manage layout teams
• Familiarity with tapeout processes, foundry collaboration, and industry best practices
• Experience with EDA tools like Virtuoso, Calibre, Synopsys IC Validator, etc.
• Excellent communication and teamwork skills